1. Field of the Invention
The present invention relates to data communication systems. More specifically, the present invention relates to systems and techniques for synchronizing data transfers across domain boundaries.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
In many data communication applications, there is a need to transfer digital data across a domain boundary. In this context, a domain is a system which operates under a single clock signal. A domain boundary then is a border between two systems operating with different clock signals. Data transfers across a boundary must be synchronized and are therefore somewhat problematic.
One technique for achieving a reliable data transfer across a domain boundary is called `speed matching`. Speed matching involves the momentary storage of the data in a first-in, first-out (FIFO) memory and the synchronous communication of control pointers thereto between the transmitting and receiving systems. The FIFO serves as a delay buffer to hold the data until the receiving system can accept the data.
Many FIFO designs are known in the art. In a conventional ripple FIFO memory, data is stored in a pipeline memory and exits after some predetermined number of clocks in first-in, first-out format. Pipeline FIFOs limit the rate at which data may be stored to the rate at which it is read. This "fall-through" delay is equal to the depth of the FIFO. Hence, ripple FIFOs tend to have large fall-through delays and suffer from synchronization problems.
An alternative FIFO design provides a write side into which data is written and a read side from which data is read. In this more popular design, a pointer is used on each side to keep track of the amount of data put in or taken out of the memory. Data is available on the feed side after one clock cycle. While this design tends to suffer less fall-through delay, synchronization problems often persist.
In any event, in these speed matching systems, the size or depth of the memory is an important consideration. U.S. Pat. No. 4,873,703, entitled SYNCHRONIZING SYSTEM, issued Oct. 10, 1989 to Crandall et al. and assigned to the present assignee, the teachings of which are incorporated herein by reference, describes a particularly advantageous speed matching scheme which allows for any degree of synchronization reliability by selecting the number of cascaded synchronizers.
The synchronous communication of control. pointers across the boundary is achieved with a gray coding scheme by which only one bit changes at a time to eliminate hazards during synchronization. This allows flip-flops to be as synchronizers which seize the value associated with the control pointers on each clock cycle. However, since the clock signal is in a different time domain than the originating signal, it could violate the set up or hold time of the flip-flop and the flip-flop could go metastable. In the context, the set up time is the time required for the flip-flop to identify a triggering edge of a clock pulse.
Hence, the referenced patent teaches the use of a FIFO memory with gray encoded control pointers so that only one of the flip-flops on either the read side or the write side can go metastable. Use of a second flip-flop in accordance with a double synchronization scheme provides a full clock cycle for the flip-flop to stabilize in the event that it goes metastable. The term `metastability` refers to an erroneous output resulting from a sampling between a logical `0` state and a logical `1` state. This all helps reduce the chance of failure. The referenced patent teaches a method for determining the correct size of the FIFO to prevent unnecessary holdoff while meeting the synchronization requirement for reliability. Unnecessary holdoff occurs when a data sink and a data source are matched in speed and either sink or source are forced to hold off (even momentarily) from transferring data.
In short, there are three problems associated with the disclosed system. First, the input setup time to the FIFO is dependent on clock skew, capacitive loading (in the data stage of the FIFO) due to routing, capacitive loading due to fanout, intrinsic setup delays of flip-flops, and pad delays. (Set up time is the amount of time that the data must be stable before the triggering edge of the clock appears.) Most of these can be controlled by design, buffer and component selection. However, capacitive loading due to fanout is normally a function of the size of the FIFO. The larger the FIFO, the larger the capacitive load, and thus the larger the setup time requirement.
Secondly, the output delay time from the FIFO is dependent on clock skew, capacitive loading (in the data stage of the FIFO) due to routing, capacitive loading due to fanout, and intrinsic delays of flip-flops, multiplexors (or tristate bus delays), and pads. Most of these can be controlled by design, buffer and component selection. However, intrinsic delay through multiplexors or tristate bus loading are a function of the size of the FIFO. Hence, the larger the FIFO, the larger intrinsic delay through the multiplexor or the larger the delay on the shared tri-state bus.
Thirdly, the overall operational speed of the FIFO is normally dependent on pad delays in combination with the propagation delay of the combinatorial logic in the control section of the FIFO. In large FIFOs, this propagation delay is a significant limitation on the speed of the overall system.
Thus, there is a need in the art for further improvements in the systems and techniques for effecting synchronous data transfers across domain boundaries with minimal error.